gnu make - Makefile: get prerequisites of target prerequisites -

is there native makefile (gnu make, etc.) way prerequisites of target prerequisites? these question not dependency check source files compiler (g++ -mm, example).

can't find on subject. , can see, there no special variables case.

to illustrate problem, here definition of compilation recipe c++ source object, pretty standard though:

##### universal compile ##### %.o: %.cpp %.hpp    ${cc} ${cflags} -c $< -o $@ 

and need build big chains of dependencies:

a: a.o b: b.o a.o c: c.o b.o a.o d: d.o c.o b.o a.o etc, n times... 

it necessary because of linking recipe:

##### universal link ##### %: %.o    ${ln} ${lnflags} $^ -o $@ 

as can see, recipe takes all of supplied dependencies, need all dependencies of supplied dependencies.

there no problem overall program linking, in recipe:

##### program link ###### ${bin}: ${obj}    ${ln} ${lnflags} ${obj} -o ${bindir}/$@ 

but need unit-testing, , units depends 1 on each others dependencies , hierarchy of testing subsystems tiring write dependency chains hard-coded.

maybe i'm doing in wrong way? maybe there alternatives link recipe? thanks!

you're doing in wrong way. why want declare b.o must recompiled every time a.o changes (that's (one of) things means when specify prerequisite pf b.o : a.o)? that's not needs happen , doesn't make sense.

you need list all object files prerequisites of single executable file, example:

exe: a.o b.o c.o d.o ... 

that's it.