primes - How to test primality in Verilog? -
i have verilog code shown below, , if try compile error message. point i'm trying manipulate input, long know cannot done in verilog. point need check following condition in verilog:
static int prime(unsigned long long n) { unsigned long long val = 1; unsigned long long divisor = 5; if (n == 2 || n == 3) return 1; if (n < 2 || n%2 == 0 || n%3 == 0) return 0; ( ; divisor<=n/divisor; val++, divisor=6*val-1) { if (n%divisor == 0 || n%(divisor+2) == 0) return 0; } return 1; } at moment have following code:
module prime(clk, rst, start, a, ready, p); input clk, rst, start; input [7:0] a; output ready, p; reg ready, p; wire [7:0] divisor; assign divisor = 5; wire [7:0] val; assign val = 1; @ (posedge clk or posedge rst) begin if (!rst) begin p <= 0; end else if (start) begin case (a) 0 : p <= 1; 1 : p <= 1; 2 : p <= 1; 3 : p <= 1; endcase if (a%2 == 0 && != 2) begin p <= 0; end else begin for( ; divisor <= a/divisor; val=val+1, divisor=6*val-1) begin if (a%divisor == 0 || a%(divisor+2) == 0) begin p <= 0; end end // need set p 1 end end end endmodule please note need test primes in form of 6n+1 or 6n-1, , need assume in code 0 , 1 primes.
if try above code error message saying:
enhanced loop not enabled verilog
if can me solve error , finish logic in verilog, glad.
the verilog bnf not allow empty or compound statements in for(;;). change file *.sv compile under systemverilog rules. otherwise change loop statement have simple statements
for( divisor =5; divisor <= a/divisor; divisor=6*val-1) begin if (a%divisor == 0 || a%(divisor+2) == 0) begin p <= 0; end val++; end also, can't make procedural assignments wires. make them variables.
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